#define SATA_REG_BASE OXNAS_HW_PA_TO_VA(0x05900000) #define SATA_PHY_BASE OXNAS_HW_PA_TO_VA(0x04900000) #define SATA_PHY_BASE_PA 0x44900000 #define SATA_REG_BASE_PA 0x45900000 #define SATA0_REGS_BASE (SATA_REG_BASE + 0x00000) #define SATA1_REGS_BASE (SATA_REG_BASE + 0x10000) #define OX820SATA_SGDMA_CORESIZE (0x10) #define OX820SATA_SGDMA_BASE0 ((u32* )(SATASGDMA_REGS_BASE + (0 * OX820SATA_SGDMA_CORESIZE))) #define OX820SATA_SGDMA_BASE1 ((u32* )(SATASGDMA_REGS_BASE + (1 * OX820SATA_SGDMA_CORESIZE)))
The more I dig around, the more the described entry from bodhi seems accurate.
This only real difference I see is that you need to have the port @ 0x45910000, and they appear to have the same DMA/SGDMA/etc.
https://github.com/mibodhi/u-boot-oxnas/blob/oxnas/drivers/block/plxsata_ide.c
https://github.com/mibodhi/u-boot-oxnas/blob/oxnas/arch/arm/include/asm/arch-nas782x/hardware.h